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5345b?hirel?02/04 features 3000 dhrystone 2.1 mips at 1.3 ghz selectable bus clock (30 cpu bus dividers up to 28x) 13 selectable core-to-l3 frequency divisors selectable mpx/60x interface voltage (1.8v, 2.5v) selectable l3 interface of 1.8v or 2.5v p d typical 12.6w at 1 ghz at v dd = 1.3v; 8.3w at 1 ghz at v dd = 1.1v, full operating conditions nap, doze and sleep modes for power saving superscalar (four instructions fetched per clock cycle) 4 gb direct addressing range virtual memory: 4 hexabytes (2 52 ) 64-bit data and 32-bit address bus interface integrated l1: 32 kb instruction and 32 kb data cache integrated l2: 512 kb 11 independent execution units and three register files write-back and write-through operations f int max = 1 ghz (1.2 ghz to be confirmed) f bus max = 133 mhz/166 mhz description this document is primarily concerned with the powerpc ? pc7457; however, unless otherwise noted, all information here also applies to the PC7447. the pc7457 and PC7447 are implementations of the powerpc microprocessor family of reduced instruction set computer (risc) microproc essors. this document describes pertinent electrical and physical characteristics of the pc7457. the pc7457 is the fourth implementation of the fourth generation (g4) microproces- sors from motorola. the pc7457 implements the full powerpc 32-bit architecture and is targeted at networking and computing systems applications. the pc7457 consists of a processor core, a 512 kbyte l2, and an internal l3 tag and controller which sup- port a glueless backside l3 cache through a dedicated high-bandwidth interface. the PC7447 is identical to the pc7457 except it does not support the l3 cache interface. the core is a high-performance superscalar design supporting a double-precision floating-point unit and a simd multimedia unit. the memory storage subsystem sup- ports the mpx bus interface to main memory and other system resources. the l3 interface supports 1, 2, or 4m bytes of external sram for l3 cache and/or private memory data. for systems implementing 4m bytes of sram, a maximum of 2m bytes may be used as cache; the remaining 2m bytes must be private memory. note that the pc7457 is a footprint-compatible, drop-in replacement in a pc7455 application if the core power supply is 1.3v. powerpc 7457 risc microprocessor pc7457/47 preliminary specification -site rev. 5345b?hirel?02/04
2 pc7457/47 [preliminary] 5345b?hirel?02/04 screening cbga upscreenings based on atmel standards full military temperature range (t j = -55 c, +125 c), industrial temperature range (t j = -40 c, +110 c) cbga package, hitce package for the 7447 tbc g suffix cbga 360 ceramic ball grid array gh suffix hitce 360 ceramic ball grid array (tbc) cbga 483
3 pc7457/47 [preliminary] 5345b?hirel?02/04 block diagram figure 1. pc7457 microprocesso r block diagram + integer reservation station unit 2 + integer reservation station unit 2 additional features - time base counter/decrementer - clock multiplier - jtag/cop interface - thermal/power management - performance monitor pa instruction unit instruction queue (12-w ord) 96-bit (3 instructions) reservation 128-bit (4 instructions) 32-bit fpscr fpscr + x floating- point unit 64-bit reservation 32-bit completion unit completion queue (16-entry) 32-kbyte d cache 36-bit 64-bit stations (2) station reservation v stations (2) fpr file 16 rename buffers stations (2-entry) gpr file 16 rename buffers reservation station vr file 16 rename buffers 64-bit 128-bit completes up instruction mmu srs 128-entry ibat array itlb tags 32-kbyte i cache vector touch queue vr issue fpr issue branch processing unit ctr lr btic (128-entry) bht (2048-entry) fetcher gpr issue (6-entry/3-issue) (4-entry/2-issue) (2-entr y/1-issue) dispatch unit data mmu srs (original) 128-entry dbat array dtlb 32-bit ea status l2 store queue (l2sq) vector fpu reservation station reservation v station reservation station vector integer er unit 1 vector integer er unit 2 vector permute unit line tags block 0 (32-byte) status block 1 (32-byte) memory subsystem snoop push/ interventions l1 castouts bus accumulator (4) x integer unit 2 to three per clock instructions l1 load queue (llq) l1 load miss (5) cacheable store request(1) l1 service l1 store queue (lsq) l3 cache controller (1) l3cr status tags bus accumulator block 0/1 line system bus interface l2 prefetch (3) 64-bit data (8-bit parity) external sram address bus data bus queues castout bus store queue push load queue (11) queue (9)/ queue (10) (2) notes: 1. the l3 cache interface is not implemented on the PC7447. 2. the castout queue and push queue share resources such for a combined total of 10 entries. the castout queue itself is limited to 9 entries, ensuring 1 entry will be available for a push. 512-kbyte united l2 cache controller 19-bit address (1, 2, or 4 mbytes) tags instruction fetch (2) 128-bit reservation (shadow) + load/store unit (ea calculation) finished completed stores stores load miss l1 castout l1 push vector touch engine + integer (3) unit 1
4 pc7457/47 [preliminary] 5345b?hirel?02/04 general parameters table 1 provides a summary of the general parameters of the pc7457. features this section summarizes features of the pc7457 implementation of the powerpc archi- tecture. major features of the pc7457 are as follows: high-performance, superscalar microprocessor ? as many as 4 instructions can be fetched from the instruction cache at a time ? as many as 3 instructions can be dispatched to the issue queues at a time ? as many as 12 instructions can be in the instruction queue (iq) ? as many as 16 instructions can be at some stage of execution simultaneously ? single-cycle execution for most instructions ? one instruction per clock cycle throughput for most instructions ? seven-stage pipeline control eleven independent execution units and three register files ? branch processing unit (bpu) features static and dynamic branch prediction 128-entry (32-set, four-way set-associative) branch target instruction cache (btic), a cache of branch instructions that have been encountered in branch/loop code sequences. if a target instruction is in the btic, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. typically, a fetch that hits the btic provides the first four instructions in the target stream 2048-entry branch history table (bht) with two bits per entry for four levels of prediction ? not-taken, strongly not-taken, taken, and strongly taken up to three outstanding speculative branches branch instructions that don?t update the count register (ctr) or link register (lr) are often removed from the instruction stream eight-entry link register stack to predict the target address of branch conditional to link regi ster (bclr) instructions table 1. device parameters parameter description technology 0.13 m cmos, nine-layer metal die size 9.1 mm 10.8 mm transistor count 58 million logic design fully-static packages PC7447: surface mount 360 ceramic ball grid array (cbga) pc7457: surface mount 483 ceramic ball grid array (cbga) core power supply 1.3v 500 mv dc nominal or 1.1v 50 mv (nominal, see table 3 on page 12 i/o power supply 1.8v 5% dc, or 2.5v 5% for recommended operating conditions
5 pc7457/47 [preliminary] 5345b?hirel?02/04 ? four integer units (ius) that share 32 gprs for integer operands three identical ius (iu1a, iu1b, and iu1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions iu2 executes miscellaneous instructions including the cr logical operations, integer multiplication and division in structions, and move to/from special- purpose register instructions ? five-stage fpu and a 32-entry fpr file fully ieee 754-1985-compliant fpu for both single- and double-precision operations supports non-ieee mode fo r time-critical operations hardware support for denormalized numbers thirty-two 64-bit fprs for single- or double-precision operands ? four vector units and 32-entry vector register file (vrs) vector permute unit (vpu) vector integer unit 1 (viu1) handles short-latency altivec ? integer instructions, such as vector add instructions (vaddsbs, vaddshs, and vaddsws, for example) vector integer unit 2 (viu2) handles longer-latency altivec integer instructions, such as vector mult iply add instruct ions (vmhaddshs, vmhraddshs, and vmladduhm, for example) vector floating-point unit (vfpu) ? three-stage load/store unit (lsu) supports integer, floating-point, and vector instruction load/store traffic four-entry vector touch queue (vtq) supports all four architected altivec data stream operations three-cycle gpr and altivec load late ncy (byte, half-word, word, vector) with one-cycle throughput four-cycle fpr load latency (single, double) with one-cycle throughput no additional delay for misaligned access within double-word boundary dedicated adder calculates effective addresses (eas) supports store gathering
6 pc7457/47 [preliminary] 5345b?hirel?02/04 performs alignment, normalization, and precision conversion for floating- point data executes cache control and tlb instructions performs alignment, zero padding, and sign extension for integer data supports hits under misses (multiple outstanding misses) supports both big- and little-endian modes, including misaligned little-endian accesses three issue queues fiq, viq, and giq can accept as many as one, two, and three instructions, respectively, in a cycle. in struction dispatch re quires the following: ? instructions can be dispatched only from the three lowest iq entries ? iq0, iq1, and iq2 ? a maximum of three instructions can be dispatched to the issue queues per clock cycle ? space must be available in the cq for an instruction to dispatch (this includes instructions that are assigned a space in the cq but not in an issue queue) rename buffers ? 16 gpr rename buffers ? 16 fpr rename buffers ? 16 vr rename buffers dispatch unit ? decode/dispatch stage fully decodes each instruction completion unit ? the completion unit retires an instruction from the 16-entry completion queue (cq) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending ? guarantees sequential programming model (precise exception model) ? monitors all dispatched instructions and retires them in order ? tracks unresolved branches and flushes instructions after a mispredicted branch ? retires as many as three instructions per clock cycle separate on-chip l1 instruction and data caches (harvard architecture) ? 32 kbyte, eight-way set-associative instruction and data caches ? pseudo least-recently-used (plru) replacement algorithm ? 32-byte (eight-word) l1 cache block ? physically indexed/physical tags ? cache write-back or write-through operation programmable on a per-page or per-block basis ? instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle ? caches can be disabled in software ? caches can be locked in software
7 pc7457/47 [preliminary] 5345b?hirel?02/04 ? mesi data cache coherency maintained in hardware ? separate copy of data cache tags for efficient snooping ? parity support on cache and tags ? no snooping of instruction cache except for icbi instruction ? data cache supports altivec lru and transient instructions ? critical double- and/or quad-word forwarding is performed as needed. critical quad-word forwarding is used for altivec loads and instruction fetches. other accesses use critical double-word forwarding level 2 (l2) cache interface ? on-chip, 512 kbyte, eight-way set-associative unified instruction and data cache ? fully pipelined to provide 32 by tes per clock cycle to the l1 caches ? a total nine-cycle load latency for an l1 data cache miss that hits in l2 ? plru replacement algorithm ? cache write-back or write-through operation programmable on a per-page or per-block basis ? 64-byte, two-sectored line size ? parity support on cache level 3 (l3) cache interface (not implemented on PC7447) ? provides critical double-word forwarding to the requesting unit ? internal l3 cache controller and tags ? external data srams ? support for 1, 2, and 4m bytes (mb) total sram space ? support for 1 or 2 mb of cache space ? cache write-back or write-through operation programmable on a per-page or per-block basis ? 64-byte (1 mb) or 128-byte (2 mb) sectored line size ? private memory capability for half (1 mb minimum) or all of the l3 sram space for a total of 1-, 2-, or 4-mb of private memory ? supports msug2 dual data rate (ddr) synchronous burst srams, pb2 pipelined synchronous burst srams, and pipelined (register-register) late write synchronous burst srams ? supports parity on cache and tags ? configurable core-to-l3 frequency divisors ? 64-bit external l3 data bus sustains 64-bit per l3 clock cycle separate memory management units (mmus) for instructions and data ? 52-bit virtual address; 32- or 36-bit physical address ? address translation for 4 kbyte pages, variable-sized blocks, and 256m bytes segments ? memory programmable as write-back/write-through, caching- inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis ? separate ibats and dbats (eight each) also defined as sprs
8 pc7457/47 [preliminary] 5345b?hirel?02/04 ? separate instruction and data translation lookaside buffers (tlbs) both tlbs are 128-entry, two-way set-associative, and use lru replacement algorithm tlbs are hardware- or software-reloadable (that is, on a tlb miss a page table search is performed in hardware or by system software) efficient data flow ? although the vr/lsu interface is 128 bits, the l1/l2/l3 bus interface allows up to 256 bits ? the l1 data cache is fully pipelined to provide 128 bits/cycle to or from the vrs ? l2 cache is fully pipelined to provi de 256 bits per processor clock cycle to the l1 cache ? as many as eight outstanding, out-of-order, cache misses are allowed between the l1 data cache and l2/l3 bus ? as many as 16 out-of-order transactions can be present on the mpx bus ? store merging for multiple store misse s to the same line. only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed) ? three-entry finished store queue and five-entry completed store queue between the lsu and the l1 data cache ? separate additional queues for efficient buffering of outbound data (such as castouts and write-through stores) from the l1 data cache and l2 cache multiprocessing support features include the following: ? hardware-enforced, mesi cache coherency protocols for data cache ? load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations power and thermal management ? 1.6v processor core ? the following three power-saving modes are available to the system: nap?instruction fetching is halted. only those clocks for the time base, decrementer, and jtag logic remain running. the part goes into the doze state to snoop memory operations on the bus and then back to nap using a qreq/qack processor-system handshake protocol sleep?power consumption is further reduced by disabling bus snooping, leaving only the pll in a locked and running state. all internal functional units are disabled deep sleep? when the part is in the sleep state, the system can disable the pll. the system can then disable the sysclk source for greater system power savings. power-on reset procedures for restarting and relocking the pll must be followed on exiting the deep sleep state
9 pc7457/47 [preliminary] 5345b?hirel?02/04 ? thermal management facility prov ides software-controllable thermal management. thermal management is performed through the use of three supervisor-level registers and a pc7457-specific thermal management exception ? instruction cache throttling provides control of instruct ion fetching to limit power consumption performance monitor can be used to help debug system designs and improve software efficiency in-system testability and debugging fe atures through jt ag boundary-scan capability testability ? lssd scan design ? ieee 1149.1 jtag interface ? array built-in self test (abist) ? factory test only reliability and serviceability ? parity checking on system bus and l3 cache bus ? parity checking on the l2 and l3 cache tag arrays
10 pc7457/47 [preliminary] 5345b?hirel?02/04 signal description figure 2. pc7457 microprocessor signal groups notes: 1. for the pc7457, there are 19 l3_addr signals, (l3_addr[0:18]. 2. for the PC7447 and pm7457, there ar e 5 pll_cfg signals, (pll_cfg[0:4]. 18 64 8 1 2 4 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 4 1 1 1 1 1 1 1 1 pc7457 l3_addr[17:0] (1) l3-data[0:63] l3_dp[0:7] l3_vsel l3_clk[0:1] l3_echo_clk[0:3] l3_cntl[0:1] int smi mcp sreset hreset ckstp_in ckstp_out tben qreq qack bvsel bmode[0:1] pmon_in pmon_out sysclk pll_cfg[0:3] (2) pll_ext ext_qual clk_out tck tdi tdo tms trst br bg a[0:35] ap[0:4] ts tt[0:4] tbst tsiz[0:2] gbl wt ci aack artry shd0/shd1 hit dbg dti[0:3] drdy d[0:63] dp[0:7] ta tea 1 1 36 5 1 5 1 3 1 1 1 1 1 2 1 1 4 1 64 8 1 1 address arbitration address transfer address transfer attributes address transfer termination data arbitration data transfer data transfer termination l3 cache address/data l3 cache clock/control interrupts/resets processor status/control clock control test interface (jtag) av dd gnd v dd ov dd gv dd note: l3 cache interface is not supported in the pc7441, pc7445, or the PC7447
11 pc7457/47 [preliminary] 5345b?hirel?02/04 detailed specification scope this specification describes the specific requirements for the microprocessor pc7457 in compliance with atmel standard screening. applicable documents 1. mil-std-883: test methods and procedures for electronics 2. mil-prf-38535: appendix a: genera l specifications for microcircuits requirements general the microcircuits are in accordance with the applicable documents and as specified herein. design and construction terminal connections depending on the package, the terminal connections are as shown in table 16, table 3 and figure 2. absolute maximum ratings notes: 1. functional and tested operating conditions are given in table 3 on page 12. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guarant eed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: v dd /av dd must not exceed ov dd /gv dd by more than 1v during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. caution: ov dd /gv dd must not exceed v dd /av dd by more than 2v during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. bvsel must be set to 0, such that the bus is in 1.8v mode. 5. bvsel must be set to hreset or 1, such that the bus is in 2.5v mode. 6. l3vsel must be set to ?hreset (inverse of hreset ), such that the bus is in 1.5v mode. table 2. absolute maximum ratings (1) symbol characteristic maximum value unit v dd (2) core supply voltage -0.3 to 1.60 v av dd (2) pll supply voltage -0.3 to 1.60 v ov dd (3)(4) processor bus supply voltage bvsel = 0 -0.3 to 1.95 v ov dd (3)(5) bvsel = hreset or ov dd -0.3 to 2.7 v gv dd (3)(6) l3 bus supply voltage l3vsel = ?hreset -0.3 to 1.65 v gv dd (3)(7) l3vsel = 0 -0.3 to 1.95 v gv dd (3)(8) l3vsel = hreset or gv dd -0.3 to 2.7 v v in (9)(10) input voltage processor bus -0.3 to ov dd + 0.3 v v in (9)(10) l3 bus -0.3 to gv dd + 0.3 v v in jtag signals -0.3 to ov dd + 0.3 v t stg storage temperature range -55 to 150 c
12 pc7457/47 [preliminary] 5345b?hirel?02/04 7. l3vsel must be set to 0, such that the bus is in 1.8v mode. 8. l3vsel must be set to hreset or 1, such that the bus is in 2.5v mode. 9. caution: v in must not exceed ov dd or gv dd by more than 0.3v at any time including during power-on reset. 10. v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 3. recommended operating conditions notes: 1. these are the recommended and tested operating condition s. proper device operation outside of these conditions is not guaranteed. 2. this voltage is the input to the filter discussed in section ?pll power supply filtering? on page 54 and not necessarily the voltage at the av dd pin which may be reduced from v dd by the filter. 3. ?hreset is the inverse of hreset . figure 3. overshoot/undershoot voltage table 3. recommended operating conditions (1) symbol characteristic recommended value unit min max v dd core supply voltage 1.3v 50 mv or 1.1v 50 mv v av dd (2) pll supply voltage 1.3v 50 mv or 1.1v 50 mv v ov dd processor bus supply voltage bvsel = 0 1.8v 5% v ov dd bvsel = hreset or ov dd 2.5v 5% v gv dd l3 bus supply voltage l3vsel = 0 1.8v 5% v gv dd l3vsel = hreset or gv dd 2.5v 5% v gv dd (3) l3vsel = ?hreset 1.5v 5% v v in input voltage processor bus gnd ov dd v v in l3 bus gnd gv dd v v in jtag signals gnd ov dd v t j die-junction temperature -55 125 c gnd gnd ? 0.3v gnd ? 0.7v not to exceed 10% of t sysclk ov dd /gv dd + 20% ov dd /gv dd + 5% ov dd /gv dd v ih v il
13 pc7457/47 [preliminary] 5345b?hirel?02/04 the pc7457 provides several i/o voltages to support both compatibility with existing systems and migration to future systems. the pc7457 core voltage must always be pro- vided at nominal 1.3v (see table 3 for act ual recommended core voltage). voltage to the l3 i/os and processor interface i/os ar e provided through separate sets of supply pins and may be provided at the voltages sh own in table 4. the input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal hreset . the output voltage will swing fr om gnd to the maximum voltage applied to the ov dd or gv dd power pins. notes: 1. not implemented on PC7447. 2. caution: the input threshold selection must agree with the ov dd /gv dd voltages sup- plied. see notes in table 2. 3. if used, pull-down resistors should be less than 250 ? 4. applicable to l3 bus interface only. ?hreset is the inverse of hreset . 5. 1.8v i/o mode and 1.5v i/o mode are not supported in n spec at v dd = 1.1v. thermal characteristics package characteristics notes: 1. see ?thermal management information? on page 15 for more details about thermal management. 2. junction temperature is a function of on -chip power dissipation, package thermal resistance, mounting site (board) tempera- ture, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 3. per semi g38-87 and jedec jesd51-2 wit h the single-layer board horizontal. 4. per jedec jesd51-6 with the board horizontal. 5. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. boar d temperature is measured on the top surface of the board near the package. 6. thermal resistance between the die and the case top surf ace as measured by the cold plate method (mil spec-883 method 1012.1) with the calculated case temperature. the actual value of r jc for the part is less than 0.1 c/w. table 4. input threshold voltage setting bvsel signal processor bus input threshold is relative to: l3vsel signal (1) l3 bus input threshold is relative to: notes 0 1.8v 0 1.8v (2)(3)(5) ?hreset not available ?hreset 1.5v (2)(4)(5) hreset 2.5v hreset 2.5v (2) 1 2.5v 1 2.5v (2) table 5. package thermal characteristics (1) symbol characteristic value unit PC7447 pc7457 r ja (2)(3) junction-to-ambient thermal resistance, natural convection 22 20 c/w r jma (2)(4) junction-to-ambient thermal resistance, natur al convection, four-layer (2s2p) board 14 14 c/w r jma (2)(4) junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer (1s) board 16 15 c/w r jma (2)(4) junction-to-ambient thermal resistance, 200 ft ./min. airflow, four-layer (2s2p) board 11 11 c/w r jb (5) junction-to-board thermal resistance 6 6 c/w r jc (6) junction-to-case therma l resistance < 0.1 < 0.1 c/w
14 pc7457/47 [preliminary] 5345b?hirel?02/04 internal package conduction resistance for the exposed-die packaging technology, shown in table 4 on page 13, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case (a ctually top-of-die since silic on die is exposed) thermal resistance the die junction-to-ball thermal resistance figure 33 on page 58 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. figure 4. c4 package with heat sink mounted to a printed-circuit board note the internal versus external package resistance. heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. because the silicon thermal resistance is quit e small, for a first-or der analysis, the tem- perature drop in the silicon may be neglected. thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms. external resistance external resistance internal resistance radiation convection heat sink thermal interface material die/package die junction package/leads printed-circuit board radiation convection
15 pc7457/47 [preliminary] 5345b?hirel?02/04 thermal management information this section provides thermal management information for the ceramic ball grid array (cbga) package for air-cooled applications. proper thermal control design is primarily dependent on the system-level design ? the heat sink, airflow, and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods ? spring clip to holes in the printed-circuit board or pack- age, and mounting clip and screw assembly (see figure 32 on page 55); however, due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. if a spring clip is used, the spring force should not exceed 10 pounds. figure 5. package exploded cross-sectional view with several heat sink options printed-circuit board thermal interface material heat sink clip heat sink cbga package
16 pc7457/47 [preliminary] 5345b?hirel?02/04 thermal interf ace materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 5 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 32 on page 55). therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure and is recom- mended due to the high power dissipation of the pc7457. of course, the selection of any thermal interface material depends on many factors ? thermal performance require- ments, manufacturability, se rvice temperature, dielectr ic properties, cost, etc. figure 6. thermal performance of select thermal interface material heat sink selection example for preliminary heat sink sizing, the di e-junction temperature can be expressed as follows: t j = t i + t r + (r jc + r int + r sa ) p d where: t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet 0 0.5 1 1.5 2 010 203040506070 80 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
17 pc7457/47 [preliminary] 5345b?hirel?02/04 r jc is the junction-to-ca se thermal resistance r int is the adhesive or interface material thermal resistance r sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 3 on page 12. the temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material (r int ) is typically about 1.5 c/w. for example, assuming a ta of 30 c, a tr of 5 c, a cbga package r jc = 0.1, and a typical power consumption (p d ) of 18.7w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 1.5 c/w + sa ) 18.7w for this example, a r sa value of 2.1 c/w or less is required to maintain the die junction temperature below the maximum value of table 3 on page 12. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging te chnologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can ade- quately describe three-dimensional heat flow. the final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature ? airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mecha- nisms (radiation, convection, and conducti on) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. for system thermal modeling, the PC7447 and pc7457 thermal model is shown in fig- ure 4 on page 14. four volumes will be used to represent this device. two of the volumes, solder ball, and air and substrate, are modeled using the package outline size of the package. the other two, die, and bump and underfill, have the same size as the die. the silicon die sh ould be modeled 9.64 11 0.74 mm with the heat source applied as a uniform source at the bottom of the volume. the bump and underfill layer is mod- eled as 9.64 11 0.69 mm (or as a collapsed volume) with orthotropic material properties: 0.6w/(m k) in the x y-plane and 2w/(m k) in the direction of the z-axis. the substrate volume is 25 25 1.2 mm (PC7447) or 29 29 1.2 mm (pc7457), and this volume has 18w/(m k) isotropic conductivity. the solder ball and air layer is mod- eled with the same horizontal dimensions as the substrate and is 0.9 mm thick. it can also be modeled as a collapsed volume using orthotropic material properties: 0.034w/(m k) in the xy-plane direction and 3.8w/(m k) in the direction of the z-axis.
18 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 7. recommended thermal model of PC7447 and pc7457 power consumption notes: 1. these values apply for all valid processor bus and l3 bus ratios. the values do not include i/o supply power (ov dd and gv dd ) or pll supply power (av dd ). ov dd and gv dd power is system dependent, but is typically < 5% of v dd power. worst case power consumption for av dd < 3 mw 2. typical power is an average value measured at the nominal recommended vdd (see table 3 on page 12) and 65 c while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz. bump and underfill die substrate solder and air die substrate side view of model (not to scale) side view of model (not to scale) x y z conductivity value unit bump and underfill k x 0.6 w/(m x k) k y 0.6 k z 2 substrate k18 solder ball and air k x 0.034 k y 0.034 k z 3.8 table 6. power consumption for pc7457 full-power mode processor (cpu) frequency unit 600 mhz 1000 mhz 1000 mhz 1200 mhz core power supply 1.1 1.1 1.3 1.3 typical (1)(2) 5.3 8.3 15.8 17.5 w maximum (1)(3) 7.9 11.5 22.0 24.2 w nap mode typical (1)(2) 1.3 1.3 5.2 5.2 w sleep mode typical (1)(2) 1.2 1.2 5.1 5.1 w deep sleep mode (pll disabled) typical (1)(2) 1.1 1.1 5.0 5.0 w
19 pc7457/47 [preliminary] 5345b?hirel?02/04 3. maximum power is the average measured at nominal v dd and maximum operating junction temperature (see table 3 on p age 12) while running an entirely cache-resi- dent, contrived sequence of instructions wh ich keep all the execution units maximally busy. 4. doze mode is not a user-definable state; it is an intermediate state between full- power and either nap or sleep mode. as a result, power consumption for this mode is not tested. electrical characteristics static characteristics table 7 provides the dc electrical characteristics for the pc7457 . notes: 1. nominal voltages; see table 3 on page 12 for recommended operating conditions. 2. for processor bus signals, the reference is ov dd while gv dd is the reference for the l3 bus signals. 3. excludes test signals and ieee 1149.1 boundary scan (jtag) signals. 4. the leakage is measured for nominal ov dd /gv dd and v dd , or both ov dd /gv dd and v dd must vary in the same direction (for example, both ov dd and v dd vary by either +5% or -5%). 5. capacitance is periodically sampled rather than 100% tested. 6. applicable to l3 bus interface only table 7. dc electrical specifications (see table 3 on page 12 for recommended operating conditions ) symbol characteristic nominal bus voltage (1) min max unit v ih (2) input high voltage (all inputs including sysclk) 1.5 gv dd 0.65 gv dd + 0.3 v v ih 1.8 ov dd /gv dd 0.65 ov dd /gv dd + 0.3 v v ih 2.5 1.7 ov dd /gv dd + 0.3 v v il (2)(6) input low voltage (all inputs including sysclk) 1.5 -0.3 gv dd 0.35 v v il 1.8 -0.3 ov dd /gv dd 0.35 v v il 2.5 -0.3 0.7 v i in (2)(3) input leakage current, v in = gv dd /ov dd ?? 30a i tsi (2)(3)(4) high-impedance (off-state) leakage current, v in = gv dd /ov dd ?? 30 a v oh (6) output high voltage, i oh = -5 ma 1.5 ov dd /gv dd ? 0.45 ? v v oh 1.8 ov dd /gv dd ? 0.45 ? v v oh 2.5 1.8 ? v v ol (6) output low voltage, i ol = 5 ma 1.5 ? 0.45 v v ol 1.8 ? 0.45 v v ol 2.5 ? 0.6 v c in capacitance, v in = 0v, f = 1 mhz l3 interface (5) ? ?9.5pf all other inputs (5) ?8.0pf
20 pc7457/47 [preliminary] 5345b?hirel?02/04 dynamic characteristics this section provides the ac electrical characteristics for the pc7457. after fabrication, functional parts are sorted by maximum processor core frequency as shown in section ?clock ac specifications? and tested for conformance to the ac specifications for that frequency. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0:4] signals. parts are sold by maximum processor core frequency; see ?ordering information? on page 59. clock ac specifications table 8 provides the clock ac timing specific ations as defined in figure 8 and repre- sents the tested operating frequencies of the devices. the maximum system bus frequency, f sysclk , given in table 8 is considered a practical maximum in a typical sin- gle-processor system. the actual maximu m sysclk frequency for any application of the pc7457 will be a function of the ac timings of the pc745 7, the ac timings for the system controller, bus loading, printed-circuit board topo logy, trace lengths, and so forth, and may be less than the value given in table 8. table 8. clock ac timing specifications (see table 3 on page 12 for recommended operating conditions ) symbol characteristic maximum processor core frequency unit 600 mhz 867 mhz 1000 mhz v dd = 1.1v v dd = 1.1v v dd = 1.1v min max min max min max f core (1) processor frequency 500 600 500 867 500 1000 mhz f vco (1) vco frequency 1000 1200 1000 1733 1000 2000 mhz f sysclk (1)(2) sysclk frequency 33 167 33 167 33 167 mhz t sysclk (2) sysclk cycle time 6 30 6 30 6 30 ns t kr , t kf (3) sysclk rise and fall time ? 1 ? 1 ? 1 ns t khkl /t sysclk (4) sysclk duty cycle measured at ov dd /2 40 60 40 60 ? ? % sysclk jitter (5)(6) ? 150 ? 150 ? ? ps internal pll relock time (7) ?100?100? ? s symbol characteristic maximum processor core frequency unit 867 mhz 1000 mhz 1200 mhz 1267 mhz v dd = 1.3v v dd = 1.3v v dd = 1.3v v dd = 1.3v min max min max min max min max f core (1) processor frequency 600 867 600 1000 600 1200 600 1267 mhz f vco (1) vco frequency 1200 1733 1200 2000 1200 2400 1200 2534 mhz f sysclk (1)(2) sysclk frequency 33 167 33 167 33 167 33 167 mhz t sysclk (2) sysclk cycle time 6 30 6 30 6 30 6 30 ns t kr , t kf (3) sysclk rise and fall time ? 1 ? 1?1?1ns t khkl / t sysclk (4) sysclk duty cycle measured at ov dd /2 40 60 40 60 40 60 40 60 % sysclk jitter (5)(6) ?150?150?150?150ps internal pll relock time (7) ? 100 ? 100 ? 100 ? 100 s
21 pc7457/47 [preliminary] 5345b?hirel?02/04 notes: 1. caution: the sysclk fr equency and pll_cfg[0:4] settings must be chosen such th at the resulting sysclk (bus) fre- quency, cpu (core) frequency and pll (vco) frequency don?t exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:4] signal description in ?pll configuration? on page 51 for valid pll_cfg[0:4] settings 2. assumes lightly-loaded, single-processor system. 3. rise and fall times for the sysclk input measured from 0.4v to 1.4v. 4. timing is guaranteed by design and characterization. 5. this represents total input jitt er, short-term and long-term combined, and is guaranteed by design. 6. the sysclk driver?s closed loop jitter bandwidth should be <500 khz at -20 db. the bandwidth must be set low to allow cascade connected pll-based de vices to track sysclk driver s with the specified jitter. 7. relock timing is guaranteed by design and characterization. pl l-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on rese t sequence. this specification also applies when the pll has been disabled and subsequently re-enabl ed during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. figure 8 provides the sysclk input timing diagram. figure 8. sysclk input timing diagram vm = midpoint voltage (ov dd /2) sysclk vm vm vm t khkl t sysclk c v il c v ih t kr t kf
22 pc7457/47 [preliminary] 5345b?hirel?02/04 processor bus ac specifications table 9 provides the processor bus ac timing specifications for the pc7457 as defined in figure 17 on page 34 and figure 9 on page 23. timing specifications for the l3 bus are provided in section ?l3 clock ac specifications? on page 24. notes: 1. all input specifications are measur ed from the midpoint of the signal in question to the midpoint of the rising edge of the input sysclk. all output specifications are measured from the midpoi nt of the rising edge of sysclk to the midpoint of the sig- nal in question. all output timings assume a purely resistive 50 ? load (see figure 17 on page 34). input and output timings are measured at the pin; time-of-fli ght delays must be added for trace lengths, vias, and connecto rs in the system. table 9. processor bus ac timing specifications (1) (at recommended operating conditions, see table 3 on page 12.) symbol (2) parameter all speed grades unit v dd = 1.1v min v dd = 1.3v max t avkh t dvkh t ivkh t mvkh (8) input setup times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , bg , ckstp_in , dbg , dti[0:3], gbl , tt[0:3], qack , ta , tben, tea , ts , ext_qual, pmon_in , shd [0:1], bmode[0:1], bmode [0:1], bvsel, l3vsel 2.0 2.0 2.0 2 1.8 1.8 1.8 1.8 ? ? ? ? ns t axkh t dxkh t ixkh t mxkh (8) input hold times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , bg , ckstp_in , dbg , dti[0:3], gbl , tt[0:3], qack , ta , tben, tea , ts , ext_qual, pmon_in , shd [0:1] bmode[0:1], bmode [0:1], bvsel, l3vsel 0 0 0 0 0 0 0 0 ? ? ? ? ns t khav t khdv t khov output valid times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , br , ci , ckstp_in , drdy , dti[0:3], gbl , hit , pmon_out , qreq , tbst , tsiz[0:2], tt[0:3], ts , shd [0:1], wt ? ? ? ? ? ? 2 2 2 ns t khax t khdx t khox output hold times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , br , ci , ckstp_in , drdy , dti[0:3], gbl , hit , pmon_out , qreq , tbst , tsiz[0:2], tt[0:3], ts , shd [0:1], wt 0.5 0.5 0.5 0.5 0.5 0.5 ? ? ? ns t khoe sysclk to output enable 0.5 0.5 ? ns t khoz sysclk to output high impedance (all except ts , artry , shd0 , shd1 ) ??3.5 ns t khtspz (3)(4)(5) sysclk to ts high impedance after precharge ? ? 1 t sysclk t kharp (3)(5)(6)(7) maximum delay to artry /shd0 /shd1 precharge ? ? 1 t sysclk t kharpz (3)(5)(6)(7) sysclk to artry /shd0 /shd1 high impedance after precharge ??2 t sysclk
23 pc7457/47 [preliminary] 5345b?hirel?02/04 2. the symbology used for timing specificat ions herein follows the pattern of t (signal)(state)(reference)(state) for inputs and t (reference)(state)(signal)(state) for outputs. for example, t ivkh symbolizes the time input signals (i) reach the valid state (v) relative to the sysclk reference (k) going to the hi gh (h) state or inpu t setup time. and t khov symbolizes the time from sysclk (k) going high (h) until outputs (o) are valid (v) or output valid time . input hold time can be read as the time that the input sig nal (i) went invalid (x) with respect to the rising clock edge (kh) (note the position of the reference and its state for inputs) a nd output hold time can be read as the time from the rising edge (kh) until the output went invalid (ox). 3. t sysclk is the period of the external clock ( sysclk) in ns. the numbers given in the ta ble must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 4. according to the bus protocol, ts is driven only by the currently active bus master. it is asserted low then precharged high before returning to high impedance as shown in figure 10 on page 24. the nominal precharge width for ts is 0.5 t sysclk , that is, less than the minimum t sysclk period, to ensure that another master asserting ts on the following clock will not con- tend with the precharge. output valid and output hold timing is te sted for the signal asserted. out put valid time is tested for precharge.the high-impedance behavior is guaranteed by design. 5. guaranteed by design and not tested. 6. according to the bus protocol, artry can be driven by multiple bus masters through the clock period immediately following aack . bus contention is not an issue because any master asserting artry will be driving it low. any master asserting it low in the first clock following aack will then go to high impedance for one clock before precharging it high during the second cycle after the assertion of aack . the nominal precharge width for artry is 1.0 t sysclk ; that is, it should be high imped- ance as shown in figure 10 on page 24 before the fi rst opportunity for another master to assert artry . output valid and output hold timing is tested for the signal asserted. the high-impedance behavior is guaranteed by design. 7. according to the mpx bus protocol, shd0 and shd1 can be driven by multiple bus masters beginning the cycle of ts . tim- ing is the same as artry , that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. the nominal precharge width for shd0 and shd1 is 1.0 t sysclk . the edges of the precharge vary depending on the programmed ratio of core to bus (pll configurations). 8. bmode [0:1] and bvsel are mode select inputs and are sampled before and after hreset negation. these parameters represent the input setup and hold times for each sample. t hese values are guaranteed by design and not tested. these inputs must remain stable after the second samp le. see figure 9 on page 23 for sample timing. figure 9. mode input timing diagram t mvrh t mxrh hreset mode signals vm
24 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 10 provides the input/output timing diagram for the pc7457. figure 10. input/output timing diagram note: vm = midpoint voltage (ov dd /2) l3 clock ac specifications the l3_clk frequency is programmed by the l3 configuration register core-to-l3 divi- sor ratio. see table 18 on page 51 for example core and l3 frequencies at various divisors. table 10 on page 25 provides the potential range of l3_clk output ac timing specifications as defined in figure 11 on page 25. the maximum l3_clk frequency is the core frequency divided by two. given the high core frequencies available in the pc7457, however, most sram designs will be not be able to operate in this mode using current technology a nd, as a result, will select a greater core-to-l3 divisor to provide a longer l3_clk period for read and write access to the l3 srams. therefore, the typical l3_c lk frequency shown in table 10 is consid- ered to be the practical maximum in a typical system. the maximum l3_clk frequency for any application of the pc7 457 will be a function of the ac timings of the pc7457, the ac timings for the sram, bus loading, and printed-circuit board trace length, and may be greater or less than the value given in table 10. note that sysclk input jitter and l3_clk[0:1] output jitter are already comp rehended in the l3 bus ac timing specifica- tions and do not need to be separately accounted for in an l3 ac timing analysis. clock skews, where applicable, do need to be accounted for in an ac timing analysis. sysclk all inputs vm all outputs vm (except ts, all outputs ts vm t khoe artry, shd0, shd1) (except ts, artry, shd0, shd1) artry, shd0, shd1 t avkh t khav t ivkh t axkh t ixkh t khdv t khov t khax t khdx t khox t khoz t khtspz t khtsx t khtsv t khtsv t kharv t kharp t kharx t kharpz
25 pc7457/47 [preliminary] 5345b?hirel?02/04 motorola is similarly limited by system constraints and cannot perform tests of the l3 interface on a socketed part on a functional tester at the maximum frequencies of table 10. therefore, functional operation and ac timing information are tested at core-to-l3 divisors which result in l3 frequencies at 250 mhz or lower. notes: 1. the maximum l3 clock frequency (and minimum l3 clock per iod) will be system dependent. see ?l3 clock ac specifica- tions? on page 24 for an explanation that this maximum fre quency is not functionally tested at speed by motorola. the minimum l3 clock frequency and period are f sysclk and t sysclk , respectively. 2. the nominal duty cycle of th e l3 output clocks is 50% measured at midpoint voltage. 3. maximum possible skew between l3_clk0 and l3_clk1. this parameter is critical to the address and control signals which are common to both sram chips in the l3. 4. maximum possible skew between l3_clk0 and l3_echo_clk1 or between l3_clk1 and l3_echo_clk3 for pb2 or late write sram. this parameter is critical to the read data signals because the processor uses the feedback loop to latch data driven from the sram, each of which drives data based on l3_clk0 or l3_clk1. 5. guaranteed by design a nd not tested. the input jitter on sysclk affects l3 output clocks and the l3 addr ess, data and control signals equally and, therefore, is already comprehended in the ac timing and does not have to be considered in the l3 timing analysis. the clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage noise or thermal effects. this is also comprehended in the ac timing specifications and need not be considered in the l3 timing analysis. figure 11. l3_clk_out output timing diagram table 10. l3_clk output ac timing specifications at recommended operating conditions (see table 3 on page 12) symbol parameter all speed grades unit min typical max f l3_clk (1) l3 clock frequency ? 200 mhz t l3_clk (1) l3 clock cycle time ? 5 ? ns t chcl /t l3_clk (2) l3 clock duty cycle ? 50 ? % t l3cskw1 (3) l3 clock output-to-output skew (l3_clk0 to l3_clk1) ? ? 100 ps t l3cskw2 (4) l3 clock output-to-output skew (l3_clk[0:1] to l3_echo_clk[1:3]) ? ? 100 ps l3 clock jitter (5) ??75ps l3_clk0 vm t l3cr t l3cf vm vm vm l3_clk1 vm vm t l3_clk t chcl vm l3_echo_clk1 l3_echo_clk3 vm vm vm vm vm vm vm vm for pb2 or late write: t l3cskw1 t l3cskw2 t l3cskw2
26 pc7457/47 [preliminary] 5345b?hirel?02/04 l3 bus ac specifications the pc7457 l3 interface supports three different types of sram: source-synchronous, double data rate (ddr) msug2 sram, late write srams, and pipeline burst (pb2) srams. each requires a different protocol on the l3 interface and a different routing of the l3 clock signals. the type of sram is programmed in l3cr[22:23] and the pc7457 then follows the appropriate protocol for that type. the designer must connect and route the l3 signals appropriately for each type of sram. following are some observations about the l3 interface. the routing for the point-to-point signals (l3_clk[0:1], l3data[0:63], l3dp[0:7], and l3_echo_clk[0:3]) to a particular sram must be delay matched for 1m byte of sram, use l3_addr[16:0] (l3_addr[0] is lsb) for 2m bytes of sram, use l3_addr[17:0] (l3_addr[0] is lsb) no pull-up resistors are required for the l3 interface for high speed operations, l3 interface address and control signals should be a "t" with minimal stubs to the two loads; data and clock signals should be point-to-point to their single load. figure 12 shows the ac test load for the l3 interface. figure 12. ac test load for the l3 interface in general, if routing is short, delay-matched, and designed for incident wave reception and minimal reflection, there is a high pr obability that the ac timing of the pc7457 l3 interface will meet the maxi mum frequency operation of appropriately chosen srams. this is despite the pessimistic, guard-banded ac specifications (see table 12 on page 28, table 13 on page 29, and table 14 on page 32), the limitations of functional testers described in section ?l3 clock ac spec ifications? on page 24 and the uncertainty of clocks and signals which inevitably make worst-case critical path timing analysis pessimistic. more specifically, certain signals within groups should be delay-matched with others in the same group while intergroup routing is less critical. only the address and control sig- nals are common to both srams and additional timing margin is available for these signals. the double-clocked data signals are grouped with individual clocks as shown in figure 13 on page 30 or figure 15 on page 33, depending on the type of sram. for example, for the msug2 ddr sram (see figure 13); l3data[0:31], l3dp[0:3], and l3_clk[0] form a closely coupled group of outputs from the pc7457; while l3data[0:15], l3dp[0:1], and l3_echo_clk[0] form a closely coupled group of inputs. the pc7450 risc microprocessor family user?s manual refers to logical settings called "sample points" used in the synchronization of reads from the receive fifo. the compu- tation of the correct value for this setting is system-dependent and is described in the pc7450 risc microprocessor family user?s manual. three specifications are used in this calcul ation and are given in table 11 on page 27. it is essential that all three specifications ar e included in the calculations to determine the sample points as incorrect settings can resu lt in errors and unpredictable behavior. for more information, see the pc7450 risc microprocessor family user?s manual. z 0 = 50 ? r l = 50 ? ov dd / 2 output
27 pc7457/47 [preliminary] 5345b?hirel?02/04 notes: 1. this specification describes a logical offset between the internal clock edge used to launch the l3 address and control signals (this clock edge is phase-aligned with the processor clock edge) and the internal clock edge used to launch the l3_clk[n] sig- nals. with proper board routing, this of fset ensures that the l3_clk[n] edge will arrive at the sram within a valid address window and provide adequate setup and hold time. this offset is reflected in the l3 bus interface ac timing specifications, but must also be separately accounted for in th e calculation of sample points and, thus, is specified here. 2. this specification is the delay from a rising or falling edge on the internal_l3_clk signal to the corresponding rising or falling edge at the l3clk[n] pins. 3. this specification is the delay from a rising or falling edge of l3_echo_clk[n] to data valid and ready to be sampled from the fifo. effects of l3ohcr settings on l3 bus ac specifications the ac timing of the l3 interface can be adjusted using the l3 output hold control register (l3ochr). each field controls the timing for a group of signals. the ac timing specifications pre- sented herein represent the ac timing when the register contains the default value of 0x0000_0000. incrementing a field delays the associated signals, increasing the output valid time and hold time of the affected signals. in the special case of delaying an l3_clk signal, the net effect is to decrease the output valid and output hold times of all signals being latched relative to that clock signal. the amount of delay added is summa- rized in table 12 on page 28. note that these settings affect output timing parameters only and don?t impact input tim- ing parameters of the l3 bus in any way. table 11. sample points calc ulation parameters symbol parameter max unit t ac delay from processor clock to internal_l3_clk (1) 3/4 t l3_clk t co delay from internal_l3_clk to l3_clk[n] output pins (2) 3ns t eci delay from l3_echo_clk[n] to receive latch (3) 3ns
28 pc7457/47 [preliminary] 5345b?hirel?02/04 notes: 1. refer to the pc7450 risc microprocessor family us er?s manual for specific information regarding l3ohcr. 2. see table 13 on page 29 and table 14 on page 32 for more information. 3. guaranteed by design; not tested or characterized. 4. default value. 5. increasing values of l3clkn_oh delay the l3_clkn signal, ef fectively decreasing the output valid and output hold times of all signals latched relative to that clock signal by the sram; see figure 13 on page 30 and figure 15 on page 33. l3 bus ac specifications for ddr msug2 srams when using ddr msug2 srams at the l3 interface, the parts should be connected as shown in figure 13. outputs from the pc7457 are actually launched on the edges of an internal clock phase- aligned to sysclk (adjuste d for core and l3 frequency divisors). l3_clk0 and l3_clk1 are this internal clock output with 90 phase delay, so outputs are shown syn- chronous to l3_clk0 and l3_clk1. output valid times are typically negative when referenced to l3_clkn because the data is launched one-quarter period before l3_clkn to provide adequate setup time at the sram after the delay-matched address, control, data, and l3_clkn signals have propagated across the printed-wiring board. inputs to the pc7457 are source-synchronous with the cq clock generated by the ddr msug2 srams. table 12. effect of l3ohcr settings on l3 bus ac timing field name (1) affected signals value output valid time output hold time unit notes parameter symbol (2) change (3) parameter symbol (2) change (3) l3aoh l3_addr[18:0], l3_cntl[0:1] 0b00 t l3chov 0 t l3chox 0 ps (4) 0b01 +50 +50 0b10 +100 +100 0b11 +150 +150 l3clkn_oh all signals latched by sram connected to l3_clkn 0b000 t l3chov t l3chdv t l3cldv 0 t l3chox t l3chdx t l3cldx 0 (4) 0b001 -50 -50 (5) 0b010 -100 -100 (5) 0b011 -150 -150 (5) 0b100 -200 -200 (5) 0b101 -250 -250 (5) 0b110 -300 -300 (5) 0b111 -350 -350 (5) l3dohn l3_data[n:n + 7], l3_dp[n/8] 0b000 t l3chdv t l3cldv 0 t l3chdx t l3cldx 0 (4) 0b001 +50 +50 0b010 +100 +100 0b011 +150 +150 0b100 +200 +200 0b101 +250 +250 0b111 +350 +350 0b111 +350 +350
29 pc7457/47 [preliminary] 5345b?hirel?02/04 these cq clocks are received on the l3_echo_clkn inputs of the pc7457. an inter- nal circuit delays the incoming l3_echo_clkn signal such that it is positioned within the valid data window at the internal receiving latches. this delayed clock is used to capture the data into these latches which comp rise the receive fifo. this clock is asyn- chronous to all other processor clocks. this latched data is subsequently read out of the fifo synchronously to the processor clock. the time between writing and reading the data is set by using the sample point settings defined in the l3cr register. table 13 provides the l3 bus interface ac timing specifications for the configuration as shown in figure 13, assuming the timing relationships shown in figure 14 and the load- ing shown in figure 12 on page 26. notes: 1. rise and fall times for the l3_clk output are measured from 20% to 80% of g v dd . 2. for ddr, all input specifications are measured from the midpoint of the signal in question to the midpoi nt voltage of the ris - ing or falling edge of the input l3_echo_clkn (see figure 14 on page 31). input timings are measured at the pins. 3. for ddr, the input data will typically follow the edge of l3_e cho_clkn as shown in figure 14. for consistency with other input setup time specifications, this will be treated as negative input setup time. 4. t l3_clk /4 is one-fourth the period of l3_clkn. this parameter in dicates that the pc7457 can latch an input signal that is valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising) edges of l3_echo_clkn at any frequency. 5. all output specifications are measured from the midpoint voltage of the rising (or for ddr write data, also the falling) edge of l3_clk to the midpoint of the signal in que stion. the output timings are measured at the pins. all output timings assume a purely resistive 50 ? load (see figure 12 on page 26). 6. for ddr, the output data will typically lead the edge of l3_clk n as shown in figure 14 on page 31. for consistency with other output valid time specif ications, this will be treated as negative output valid time. 7. t l3_clk /4 is one-fourth the period of l3_clkn. this parameter indi cates that the specified output signal is actually launched by an internal clock delayed in phase by 90 . therefore, there is a frequency compone nt to the output valid and output hold times such that the specified ou tput signal will be valid for approximately one l3_clk period starting three-fourths of a clock prior to the edge on which the sram will sample it and ending one-fourth of a clock period after the edge it will be sampled. 8. assumes default value of l3ohcr. see ?effects of l3ohcr se ttings on l3 bus ac specifications? on page 27 for more information. table 13. l3 bus interface ac timing specifications for msug2 at recommended operating conditions (see table 3 on page 12) symbol parameter all speed grades unit min max t l3cr , t l3cf l3_clk rise and fall time (1) ?0.75ns t l3dveh , t l3dvel setup times: data and parity (2)(3)(4) -0.35 ? ns t l3dxeh , t l3dxel input hold times: data and parity (2)(4) 2.1 ? ns t l3chdv , t l3cldv valid times: data and parity (5)(6)(7)(8) ?(-t l3clk /4) + 0.60 ns t l3chov valid times: all other outputs (5)(7)(8) ?(t l3clk /4) + 0.65 ns t l3chdx , t l3cldx output hold times: data and parity (5)(6)(7)(8) (t l3clk /4) - 0.60 ? ns t l3chox output hold times: all other outputs (5)(7)(8) (t l3clk /4) - 0.50 ? ns t l3cldz l3_clk to high impedance: data and parity ? tbd ns
30 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 13 shows the typical connection diagram for the pc7457 interfaced to msug2 ddr srams. figure 13. typical source synchronous 4m bytes l3 cache ddr interface note: 1. or as recommended by sram manufacturer for single-ended clocking. {l3data[0:15], l3dp[0:1]} {l3data[16:31], l3dp[2:3]} {l3data[32:47], l3dp[4:5]} l3addr[18:0] l3_cntl[0] l3_clk[0] l3_clk[1] l3_echo_clk[0] l3_echo_clk[1] l3echo_clk[2] l3_echo_clk[3] {l3data[48:63], l3dp[6:7]} cq sa[18:0] ck b1 b2 sram 0 sram 1 cq d[0:17] d[18:35] cq sa[18:0] ck b1 b2 cq d[0:17] d[18:35] l3_cntl[1] nc nc gnd gnd gnd nc nc gnd gnd gnd pc7457 denotes receive (sram to pc7457) aligned signals denotes transmit (pc7457 to sram) aligned signals (1) cq ck b3 g cq lbo cq ck b3 g cq lbo gv dd /2 (1) gv dd /2
31 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 14 shows the l3 bus timing diagrams for the pc7457 interfaced to msug2 srams. figure 14. l3 bus timing diagrams for l3 cache ddr srams note: t l3chdv and t l3cldv as drawn here will be negative numbers, that is, output valid time will be time before the clock edge. notes: 1. t l3dveh and t l3dvel as drawn here will be negative numbers, that is, input setup time will be time after the clock edge. 2. vm = midpoint voltage (gv dd /2) l3_clk[0,1] addr, l3cntl vm t l3chov t l3chox vm t l3choz vm vm vm t l3chdv t l3chdx outputs t l3cldv t l3cldx t l3cldz l3data write l3_echo_clk[0,1,2,3] l3 data and data parity inputs vm vm vm vm vm inputs t l3dveh t l3dxel t l3dvel t l3dxeh
32 pc7457/47 [preliminary] 5345b?hirel?02/04 l3 bus ac specifications for pb2 and late write srams when using pb2 or late write srams at the l3 interface, the parts should be con- nected as shown in figure 15 on page 33. these srams are synchronous to the pc7457; one l3_clkn signal is output to each sram to latch address, control, and write data. read data is launched by the sram synchronous to the delayed l3_clkn signal it received. the pc7457 needs a copy of that delayed clock which launched the sram read data to know when the returning data will be valid. therefore, l3_echo_clk1 and l3_echo_clk3 must be routed halfway to the srams and then returned to the pc7457 inputs l3_echo _clk0 and l3_echo_clk2, respectively. thus, l3_echo_clk0 and l3_echo_clk2 are phase-aligned with the input clock received at the srams. the pc7457 will latch the incoming data on the rising edge of l3_echo_clk0 and l3_echo_clk2. table 14 provides the l3 bus interface ac timing specifications for the configuration shown in figure 15, assuming the timing re lationships of figure 16 and the loading of figure 12 on page 26. notes: 1. rise and fall times for the l3_clk output are measured from 20% to 80% of gv dd . 2. timing behavior and characterization are currently being evaluated. 3. all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input l3_echo_clkn (see figure 14 on page 31). input timings are measured at the pins. 4. all output specifications are measured fr om the midpoint voltage of the rising edge of l3_clkn to the midpoint of the signal in question. the output timings ar e measured at the pins. all output timings assume a purely resistive 50 ? load (see figure 14). 5. t l3_clk /4 is one-fourth the period of l3_clkn. this parameter indi cates that the specified output signal is actually launched by an internal clock delayed in phase by 90 . therefore, there is a frequency compone nt to the output valid and output hold times such that the specified ou tput signal will be valid for approximately one l3_clk period starting three-fourths of a clock before the edge on which the sram will sample it and ending one-fourth of a clock period after the edge it will be sampled. 6. assumes default value of l3ohcr. see ?effects of l3ohcr se ttings on l3 bus ac specifications? on page 27 for more information. table 14. l3 bus interface ac timing specifications for pb2 and late write srams at recommended operating condi- tions (see table 3 on page 12) symbol parameter all speed grades unit min max t l3cr , t l3cf l3_clk rise and fall time (1)(2) ?0.75ns t l3dveh setup times: data and parity (2)(3) 0.1 ? ns t l3dxeh input hold times: data and parity (2)(3) ?0.7ns t l3chdv valid times: data and parity (2)(4)(5)(6) ?2.5ns t l3chov valid times: all other outputs (5)(6) ?1.8ns t l3chdx output hold times: data and parity (2)(4)(5)(6) 1.4 ? ns t l3chox output hold times: all other outputs (2)(5)(6) 1.0 ? ns t l3chdz l3_clk to high impedance: data and parity (2) ?3.0ns t l3choz l3_clk to high impedance: all other outputs (2) ?3.0ns
33 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 15 shows the typical connection diagram for the pc7457 interfaced to pb2 srams or late write srams. figure 15. typical synchronous 1m byte l3 cache late write or pb2 interface note: 1. or as recommended by sram manufacturer for single-ended clocking. l3_addr[16:0] l3_cntl[0] sa[16:0] k k ss sw zz g sram 0 dq[0:17] dq[18:36 ] l3_cntl[1] gv dd /2 /2 (1) gv dd /2 (1) gnd gnd sram 1 gnd gnd l3_clk[0] l3_clk[1] l3_echo_clk[0] l3_echo_clk[1] l3_echo_clk[2] pc7457 l3_echo_clk[3] sa[16:0] k k ss sw zz g dq[0:17] dq[18:36] denotes receive (sram to pc7457) aligned signals denotes transmit (pc7457 to sram) aligned signals {l3_data[0:15], l3_dp[0:1]} {l3_data[16:31], l3_dp[2:3]} {l3_data[32:47], l3_dp[4:5]} {l3_data[48:63], l3_dp[6:7]}
34 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 16 shows the l3 bus timing diagrams for the pc7457 interfaced to pb2 or late write srams. figure 16. l3 bus timing diagrams for late write or pb2 srams note: vm = midpoint voltage (gv dd /2) figure 17. ac test load l3_echo_clk[0,2] vm t l3dveh t l3dxeh l3_clk[0,1] addr, l3_cntl vm t l3chov t l3chox vm t l3chdz outputs inputs l3_echo_clk[1,3] t l3chdv t l3chdx t l3choz l3data write parity inputs l3 data and data z 0 = 50 ? r l = 50 ? ov dd / 2 output
35 pc7457/47 [preliminary] 5345b?hirel?02/04 ieee 1149.1 ac timing specifications table 15 provides the ieee 1149.1 (jtag) ac timi ng specifications as defined in figure 19 through figure 22 on page 37. notes: 1. all outputs are measured from the mi dpoint voltage of the falling/rising edge of tclk to the midpoint of the signal in ques- tion. the output timings are measured at the pins. all output timings assume a purely resistive 50 ? load (see figure 18). time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 3. non-jtag signal input timing with respect to tck. 4. non-jtag signal output timing with respect to tck. 5. guaranteed by design and characterization figure 18 provides the ac test load for tdo and the boundary-scan outputs of the pc7457. figure 18. alternate ac test load for the jtag interface table 15. jtag ac timing specificat ions (independ ent of sysclk) (1) at recommended op erating conditions (see table 3 on page 12) symbol parameter min max unit f tclk tck frequency of operation 0 33.3 mhz t tclk tck cycle time 30 ? ns t jhjl tck clock pulse width measured at 1.4v 15 ? ns t jr and t jf tck rise and fall times 0 2 ns t trst (2) trst assert time 25 ? ns t dvjh (3) t ivjh input setup times: boundary-scan data tms, tdi 4 0 ? ? ns t dxjh (3) t ixjh input hold times: boundary-scan data tms, tdi 20 25 ? ? ns t jldv (4) t jlov valid times: boundary-scan data tdo 4 4 20 25 ns t jldx (4) t jlox output hold times: boundary-scan data tdo tbd tbd tbd tbd t jldz (4)(5) t jloz tck to output high impedance: boundary-scan data tdo 3 3 19 9 ns output z 0 = 50 ? r l = 50 ? ov dd /2
36 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 19. jtag clock input timing diagram note: vm = midpoint voltage (ov dd /2) figure 20. trst timing diagram note: vm = midpoint voltage (ov dd /2) figure 21. boundary-scan timing diagram note: vm = midpoint voltage (ov dd /2) vm vm vm t tclk t jr t jf t jhjl tclk trst t trst vm vm vm tck boundary data inputs boundary data outputs boundary data outputs t dxjh t dvjh t jldv t jldz output data valid t jldx vm input data valid output data valid
37 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 22. test access port timing diagram note: vm = midpoint voltage (ov dd /2) preparation for delivery handling mos devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge. input protection devices have been designed in the chip to minimize the effect of static buildup. however, the following handling practices are recommended: devices should be handled on benches with conductive and grounded surfaces. ground test equipment, tools and operator. do not handle devices by the leads. store devices in conduc tive foam or carriers. avoid use of plastic, rubber or silk in mos areas. maintain relative humidity above 50% if practical. t jlox input data valid t ivjh t ixjh t jlov t jloz output data valid output data valid vm tck tdi, tms tdo tdo vm
38 pc7457/47 [preliminary] 5345b?hirel?02/04 package mechanical data the following sections provide the package parameters and mechanical dimensions for the cbga package. package parameters for the PC7447, 360 cbga the package parameters are as provided in the following list. the package type is 25 25 mm, 360-lead ceramic ball grid array (cbga). package outline 25 mm 25 mm interconnects 360 (19 19 ball array - 1) pitch 1.27 mm (50 mil) minimum module height 2.72 mm maximum module height 3.24 mm ball diameter 0.89 mm (35 mil)
39 pc7457/47 [preliminary] 5345b?hirel?02/04 pin assignment figure 23 shows the pinout of the PC7447, 360 cbga package as viewed from the top surface. figure 24 shows the side profile of the cbga package to indicate the direction of the top surface view. figure 23. pinout of the PC7447, 360 cbga package as viewed from the top surface figure 24. side view of the cbga package a b c d e f g h j k l m n p r t 3 2 1456 16 17 18 19 u v w 15 14 13 12 11 10 9 8 7 substrate assembly encapsulant view die
40 pc7457/47 [preliminary] 5345b?hirel?02/04 pinout listings table 16 provides the pinout listing for the PC7447, 360 cbga package. table 15 pro- vides the pinout listing for the pc7457, 483 cbga package. note: this pinout is not compatible with th e pc750, pc7400, or pc7410 360 bga package. table 16. pinout listing for the PC7447, 360 cbga package signal name pin number active i/o i/f select (1) a[0:35] (2) e11, h1, c11, g3, f10, l2, d11, d1, c10, g2, d12, l3, g4, t2, f4, v1, j4, r2, k5, w2, j2, k4, n4, j3 , m5, p5, n3, t1, v2, u1, n5, w1, b12, c4, g10, b11 high i/o bvsel aack r1 low input bvsel ap[0:4] c1, e3, h6, f5, g7 high i/o bvsel artry (3) n2 low i/o bvsel av dd a8 ? input bvsel bg m1 low input bvsel bmode0 (4) g9 low input bvsel bmode1 (5) f8 low input bvsel br d2 low output bvsel bvsel (1)(6) b7 high input bvsel ci (3) j1 low output bvsel ckstp_in a3 low input bvsel ckstp_out b1 low output bvsel clk_out h2 high output bvsel d[0:63] r15, w15, t14, v16, w1 6, t15, u15, p14, v13, w13, t13, p13, u14, w14, r12, t12, w12, v12, n11, n1 0, r11, u11, w11, t11, r10, n9, p10, u10, r9, w10, u9, v9, w5, u6, t5, u5, w7, r6, p7, v6, p17, r19, v18, r18, v19, t19, u19, w19, u18, w17, w18, t16, t18, t17, w3, v17, u4, u8, u7, r7, p6, r8, w8, t8 high i/o bvsel dbg m2 low input bvsel dp[0:7] t3, w4, t4, w9, m6, v3, n8, w6 high i/o bvsel drdy (7) r3 low output bvsel dti[0:3] (8) g1, k1, p1, n1 high input bvsel ext_qual (9) a11 high input bvsel gbl e2 low i/o bvsel gnd b5, c3, d6, d13, e17, f3, g17, h4 , h7, h9, h11, h13, j6, j8, j10, j12, k7, k3, k9, k11, k13, l6, l8, l10, l12, m4, m7, m9, m11, m13, n7, p3, p9, p12, r5, r14, r17, t7, t10, u3, u13, u17, v5, v8, v11, v15 ?? n/a hit (7) b2 low output bvsel hreset d8 low input bvsel int d4 low input bvsel l1_tstclk (9) g8 high input bvsel l2_tstclk (10) b3 high input bvsel
41 pc7457/47 [preliminary] 5345b?hirel?02/04 no connect (11) a6, a13, a14, a15, a16, a17, a18, a19, b13, b14, b15, b16, b17, b18, b19, c13, c14, c15, c16, c17, c18, c19, d14, d15, d16, d17, d18, d19, e12, e13, e14, e15, e16, e19, f12, f13, f14, f15, f16, f17, f18, f19, g11, g 12, g13, g14, g15, g16, g19, h14, h15, h16, h17, h18, h19, j14, j15, j16, j17, j18, j19, k15, k16, k17, k18, k19, l14, l15, l16, l17, l18, l19, m14, m15, m16, m17, m18, m19, n12, n13, n14, n15, n16, n17, n18, n19, p15, p16, p18, p19 ?? ? lssd_mode (6)(12) e8 low input bvsel mcp c9 low input bvsel ov dd b4, c2, c12, d5, e18, f2, g18, h3 , j5, k2, l5, m3, n6, p2, p8, p11, r4, r13, r16, t6, t9, u2, u12, u16, v4, v7, v10, v14 ?? n/a pll_cfg[0:4] b8, c8, c7, d7, a7 high input bvsel pmon_in (13) d9 low input bvsel pmon_out a9 low output bvsel qack g5 low input bvsel qreq p4 low output bvsel shd [0:1] (3) e4, h5 low i/o bvsel smi f9 low input bvsel sreset a2 low input bvsel sysclk a10 ? input bvsel ta k6 low input bvsel tben e1 high input bvsel tbst f11 low output bvsel tck c6 high input bvsel tdi (6) b9 high input bvsel tdo a4 high output bvsel tea l1 low input bvsel test[0:3] (12) a12, b6, b10, e10 ? input bvsel test[4] (9) d10 ? input bvsel tms (6) f1 high input bvsel trst (6)(14) a5 low input bvsel ts (3) l4 low i/o bvsel tsiz[0:2] g6, f7, e7 high output bvsel tt[0:4] e5, e6, f6, e9, c5 high i/o bvsel wt (3) d3 low output bvsel v dd h8, h10, h12, j7, j9, j11, j13, k8 , k10, k12, k14, l7, l9, l11, l13, m8, m10, m12 ?? n/a table 16. pinout listing for the PC7447, 360 cbga package (continued) signal name pin number active i/o i/f select (1)
42 pc7457/47 [preliminary] 5345b?hirel?02/04 notes: 1. ov dd supplies power to the processor bus, jtag, and all control signals; and v dd supplies power to the processor core and the pll (after filtering to become av dd ). to program the i/o voltage, connect bvsel to either gnd (selects 1.8v) or to hreset (selects 2.5v). if used, the pull- down resistor should be less than 250 ? . for actual recommended value of v in or supply voltages see figure 3 on page 12 . 2. unused address pins must be pulled down to gnd. 3. these pins require weak pull-up resistors (for example, 4.7 k ? ) to maintain the control signals in the negated state after they have been actively negated and released by the PC7447 and other bus masters. 4. this signal selects between mpx bus mode (asserted) and 60x bus mode (negated) and will be sampled at hreset going high. 5. this signal must be negated during reset, by pull up to ov dd or negation by ?hreset (inverse of hreset ), to ensure proper operation. 6. internal pull up on die. 7. ignored in 60x bus mode. 8. these signals must be pulled down to gnd if unused, or if the PC7447 is in 60x bus mode. 9. these input signals are for factory use only and must be pulled down to gnd for normal machine operation. 10. it is recommended this test signal be tied to hreset ; however, other configurations will not adversely affect performance. 11. these signals are for factory use only and must be left unconnected for normal machine operation. 12. these input signals are for factory use only and must be pulled up to ov dd for normal machine operation. 13. this pin can externally cause a performance monitor event. counting of the event is enabled via software. 14. this signal must be asserted during reset, by pull down to gnd or assertion by hreset , to ensure proper operation
43 pc7457/47 [preliminary] 5345b?hirel?02/04 mechanical dimensions for the PC7447, 360 cbga figure 25 provides the mechanical dimensions and bottom surface nomenclature for the PC7447, 360 cbga package. figure 25. mechanical dimensions and bottom surface nomenclature for the PC7447, 360 cbga package notes: 1. dimensioning and tolerance per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metallized feature with various sh apes. bottom side a1 corner is designated with a ball missing from the array c a 360x a b c d e f g h j k l m n p r t b 0.3 c 0.15 b u w v 123456 789101112131415161718 19 0.2 2x c a1 corner b 0.2 2x d e e3 e2 e1 e4 d2 d4 d3 d1 capacitor region 1 a 0.15 a 0.35 a a a1 a2 a3 millimeters dim min max a 2.72 3.20 a1 0.80 1 a2 1.10 1.30 a3 ? 0.6 b 0.82 0.93 d 25 bsc d1 ? 11.3 d2 8 ? d3 ? 6.5 d4 10.9 11.1 e 1.27 bsc e 25 bsc e1 ? 11.3 e2 8 ? e3 ? 6.5 e4 9.55 9.75
44 pc7457/47 [preliminary] 5345b?hirel?02/04 substrate capacitors fo r the PC7447, 360 cbga figure 26 shows the connectivity of the substrate capacitor pads for the PC7447, 360 cbga. all capacitors are 100 nf. figure 26. substrate bypass capacitors for the PC7447, 360 cbga package parameters for the pc7457, 483 cbga the package parameters are as provided in the following list. the package type is 29 29 mm, 483-lead ceramic ball grid array (cbga). package outline 29 mm 29 mm interconnects 483 (22 22 ball array - 1) pitch 1.27 mm (50 mil) minimum module height ? maximum module height 3.22 mm ball diameter 0.89 mm (35 mil) 1 c1-2 c1-1 c2-1 c3-1 c4-1 c5-1 c6-1 c6-2 c5-2 c4-2 c3-2 c2-2 c18-1 c18-2 c17-2 c16-2 c15-2 c14-2 c13-2 c13-1 c14-1 c15-1 c16-1 c17-1 c12-1 c12-2 c11-2 c10-2 c9-2 c8-2 c7-2 c7-1 c8-1 c9-1 c10-1 c11-1 c19-2 c19-1 c20-1 c21-1 c22-1 c23-1 c24-1 c24-2 c23-2 c22-2 c21-2 c20-2 a1 corner c1 gnd v dd c2 gnd v dd c3 gnd ov dd c4 gnd v dd c5 gnd v dd c6 gnd v dd c7 gnd v dd c8 gnd v dd c9 gnd ov dd c10 gnd v dd c11 gnd v dd c12 gnd v dd c13 gnd v dd c14 gnd v dd c15 gnd v dd c16 gnd ov dd c17 gnd v dd c18 gnd ov dd c19 gnd v dd c20 gnd v dd c21 gnd ov dd c22 gnd v dd c23 gnd v dd c24 gnd v dd capacitor pad number -1 -2
45 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 27 shows the pinout of the pc7457, 483 cbga package as viewed from the top surface. figure 28 shows the side profile of the cbga package to indicate the direction of the top surface view. figure 27. pinout of the pc7457, 483 cbga package as viewed from the top surface figure 28. side view of the cbga package a b c d e f g h j k l m n p r t 123456789101112131415 16 17 18 19 u v w 20 21 22 y aa ab encapsulant substrate assembly view die
46 pc7457/47 [preliminary] 5345b?hirel?02/04 . table 17. pinout listing for the pc7457, 483 cbga package signal name pin number active i/o i/f select (1) a[0:35] (2) e10, n4, e8, n5, c8, r2, a7, m2, a6, m1, a10, u2, n2, p8, m8, w4, n6, u6, r5, y4, p1, p4, r6, m7 , n7, aa3, u4, w2 , w1, w3, v4, aa1, d10, j4, g10, d9 high i/o bvsel aack u1 low input bvsel ap[0:4] l5, l6, j1, h2, g5 high i/o bvsel artry (3) t2 low i/o bvsel avdd b2 ? input n/a bg r3 low input bvsel bmode0 (4) c6 low input bvsel bmode1 (5) c4 low input bvsel br k1 low output bvsel bvsel (6)(7) g6 high input n/a ci (3) r1 low output bvsel ckstp_in f3 low input bvsel ckstp_out k6 low output bvsel clk_out n1 high output bvsel d[0:63] ab15, t14, r14, ab13, v14, u14, ab14, w16, aa11, y11, u12, w13, y14, u13, t12, w12, ab12, r12, aa13, ab11, y12, v11, t11, r11, w10, t10, w11, v10, r10, u10, aa10, u9, v7, t8, ab4, y6, ab7, aa6, y8, aa7, w8, ab10, aa1 6, ab16, ab17, y18, ab18, y16, aa18, w14, r13, w15, aa14, v16, w6, aa12, v6, ab9, ab6, r7, r9, aa9, ab8, w9 high i/o bvsel dbg v1 low input bvsel dp[0:7] aa2, ab3, ab2, aa8, r8, w5, u8, ab5 high i/o bvsel drdy (8) t6 low output bvsel dti[0:3]) (9) p2, t5, u3, p6 high input bvsel ext_qual (10) b9 high input bvsel gbl m4 low i/o bvsel gnd a22, b1, b5, b12, b14, b16, b18, b20, c3, c9, c21, d7, d13, d15, d17, d19, e2, e5, e21, f10, f12, f14, f16, f19, g4 , g7, g17, g21, h13, h15, h19, h5, j3, j10, j12, j14, j17, j21, k5, k9, k11, k13, k15, k19, l10, l12, l14, l17, l21, m3, m6, m9, m11, m13, m19, n10, n12, n14, n17, n21, p3, p9, p11, p13, p15, p19, r17, r21, t13, t15, t19, t4, t7, t9, u17, u21, v2, v5, v8, v12, v15, v19, w7, w17, w21, y3, y9, y13, y15, y20, aa5, aa17, ab1, ab22 ?? n/a gv dd (11) b13, b15, b17, b19, b21, d12, d14, d16, d18, d21, e19, f13, f15, f17, f21, g19, h12, h1 4, h17, h21, j19, k17, k21, l19, m17, m21, n19, p17, p21, r15, r19, t17, t21, u19, v17, v21, w19, y21 ?? n/a hit (8) k2 low output bvsel hreset a3 low input bvsel
47 pc7457/47 [preliminary] 5345b?hirel?02/04 signal name pin number active i/o i/f select (1) int j6 low input bvsel l1_tstclk (10) h4 high input bvsel l2_tstclk (12) j2 high input bvsel l3vsel (6)(7) a4 high input n/a l3addr[18:0] h11, f20, j16, e22, h18, g20, f22, g22, h20, k16, j18, h22, j20, j22, k18, k20, l16, k22, l18 high output l3vsel l3_clk[0:1] v22, c17 high output l3vsel l3_cntl [0:1] l20, l22 low output l3vsel l3data[0:63] aa19, ab20, u16, w18, aa20, ab21, aa21, t16, w20, u18, y22, r16, v20, w22, t18, u20, n18, n20, n16, n22, m16, m18, m20, m22, r18, t20, u22, t22, r20, p18, r22, m15, g18, d22, e20, h16, c22, f18, d20, b22, g16, a21, g15, e17, a20, c19, c18, a19, a18, g14, e15, c16, a17, a16, c15, g13, c14, a14, e13, c13, g12, a13, e12, c12 high i/o l3vsel l3dp[0:7] ab19, aa22, p22, p16, c20, e16, a15, a12 high i/o l3vsel l3_echo_clk[0,2] v18, e18 high input l3vsel l3_echo_clk[1,3] p20, e14 high i/o l3vsel lssd_mode (7)(13) f6 low input bvsel mcp b8 low input bvsel no connect (14) a8, a11, b6, b11, c11, d11, d3, d5, e11, e7, f2, f11, g2, h9 ? ? n/a ov dd b3, c5, c7, c10, d2, e3, e9, f5, g3, g9, h7, j5, k3, l7, m5, n3, p7, r4, t3, u5, u7, u11, u15, v3, v9, v13, y2, y5, y7, y10, y17, y19, aa4, aa15 ?? n/a pll_cfg[0:4] a2, f7, c2 , d4, h8 high input bvsel pmon_in (15) e6 low input bvsel pmon_out b4 low output bvsel qack k7 low input bvsel qreq y1 low output bvsel shd [0:1] l4, l8 low i/o bvsel smi g8 low input bvsel sreset g1 low input bvsel sysclk d6 ? input bvsel ta n8 low input bvsel tben l3 high input bvsel tbst b7 low output bvsel tck j7 high input bvsel tdi (7) e4 high input bvsel tdo h1 high output bvsel tea t1 low input bvsel table 17. pinout listing for the pc7457, 483 cbga package (continued)
48 pc7457/47 [preliminary] 5345b?hirel?02/04 notes: 1. ov dd supplies power to the processor bus, jtag, and all control signals except the l3 cache controls (l3ctl[0:1]); gv dd supplies power to the l3 cache interface (l3addr[0:17], l3da ta[0:63], l3dp[0:7], l3_echo _clk[0:3], and l3_clk[0:1]) and the l3 control signals l3_cntl [0:1]; and v dd supplies power to the processor core and the pll (after filtering to become av dd ). for actual recommended value of v in or supply voltages, see table 3 on page 12. 2. unused address pins must be pulled down to gnd. 3. these pins require weak pull-up resistors (for example, 4.7 k ? ) to maintain the control signals in the negated state after they have been actively negated and released by the pc7457 and other bus masters. 4. this signal selects between mpx bus mode (asserted) and 60x bus mode (negated) and will be sampled at hreset going high. 5. this signal must be negated during reset, by pull up to ov dd or negation by ?hreset (inverse of hreset ), to ensure proper operation. 6. to program the processor interface i/o voltage, conne ct bvsel to either gnd (selects 1.8v) or to hreset (selects 2.5v). to program the l3 interface, connect l3vsel to either gnd (selects 1.8v) or to hreset (selects 2.5v). if used, pull-down resistors should be less than 250 ? . 7. internal pull up on die. 8. ignored in 60x bus mode. 9. these signals must be pulled down to gnd if unused or if the pc7457 is in 60x bus mode. 10. these input signals for factory use only and must be pulled down to gnd for normal machine operation. 11. power must be supplied to gv dd , even when the l3 interface is disabled or unused. 12. it is recommended that this test signal be tied to hreset ; however, other configurations will not adversely affect performance. 13. these input signals are for factory use only and must be pulled up to ov dd for normal machine operation. 14. these signals are for factory use only and must be left unconnected for normal machine operation. 15. this pin can externally cause a performance monitor event. counting of the event is enabled via software. 16. this signal must be asserted during reset, by pull down to gnd or assertion by hreset , to ensure proper operation. 17. these pins are internally connected to v dd . they are intended to allow an external device to detect the core voltage level present at the processor core. if unused , they must be connected directly to v dd or left unconnected. signal name pin number active i/o i/f select (1) test[0:5] (13) b10, h6, h10, d8, f9, f8 ? input bvsel test[6] (10) a9 ? input bvsel tms (7) k4 high input bvsel trst (7)(16) c1 low input bvsel ts (3) p5 low i/o bvsel tsiz[0:2] l1,h3,d1 high output bvsel tt[0:4] f1, f4, k8, a5, e1 high i/o bvsel wt (3) l2 low output bvsel v dd j9, j11, j13, j15, k10, k12, k1 4, l9, l11, l13, l15, m10, m12, m14, n9, n11, n13, n15, p10, p12, p14 ?? n/a vdd_sense[0:1] (17) g11, j8 ? ? n/a table 17. pinout listing for the pc7457, 483 cbga package (continued)
49 pc7457/47 [preliminary] 5345b?hirel?02/04 mechanical dimensions for the pc7457, 483 cbga figure 25 provides the mechanical dimensions and bottom surface nomenclature for the pc7457, 483 cbga package. figure 29. mechanical dimensions and bottom surface nomenclature for the pc7457, 483 cbga package notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metallized feature with various shapes. bottom side. a1 corner is designated with a ball miss- ing from the array c a 483x a b c d e f g h j k l m n p r t b 0.3 c 0.15 b u w v y ab aa 123456 789101112131415161718192021 22 capacitor region a 0.15 a 0.35 a a a1 a2 a3 millimeters dim min max a 2.72 3.20 a1 0.80 1 a2 1.10 1.30 a3 ? 0.6 b 0.82 0.93 d 29 bsc d1 ? 12.5 d2 8.5 ? d3 ? 8.4 d4 10.9 11.1 e 1.27 bsc e 29 bsc e1 ? 12.5 e2 8.5 ? e3 ? 8.4 e4 9.55 9.75 0.2 2x c a1 corner b 0.2 2x d e e3 e2 e1 e4 d2 d4 d3 d1 1
50 pc7457/47 [preliminary] 5345b?hirel?02/04 substrate capacitors fo r the pc7457, 483 cbga figure 26 shows the connectivity of the substrate capacitor pads for the pc7457, 483 cbga. all capacitors are 100 nf. figure 30. substrate bypass capacitors for the pc7457, 483 cbga 1 c1-2 c1-1 c2-1 c3-1 c4-1 c5-1 c6-1 c6-2 c5-2 c4-2 c3-2 c2-2 c18-1 c18-2 c17-2 c16-2 c15-2 c14-2 c13-2 c13-1 c14-1 c15-1 c16-1 c17-1 c12-1 c12-2 c11-2 c10-2 c9-2 c8-2 c7-2 c7-1 c8-1 c9-1 c10-1 c11-1 c19-2 c19-1 c20-1 c21-1 c22-1 c23-1 c24-1 c24-2 c23-2 c22-2 c21-2 c20-2 a1 corner c1 gnd ov dd c2 gnd v dd c3 gnd gv dd c4 gnd v dd c5 gnd v dd c6 gnd gv dd c7 gnd v dd c8 gnd v dd c9 gnd gv dd c10 gnd v dd c11 gnd v dd c12 gnd gv dd c13 gnd v dd c14 gnd v dd c15 gnd v dd c16 gnd ov dd c17 gnd v dd c18 gnd ov dd c19 gnd v dd c20 gnd v dd c21 gnd ov dd c22 gnd v dd c23 gnd v dd c24 gnd v dd capacitor pad number -1 -2
51 pc7457/47 [preliminary] 5345b?hirel?02/04 system design information this section provides system and thermal design recommendations for successful appli- cation of the pc7457. pll configuration the pc7457 pll is co nfigured by the pll_ cfg[0:4] signals. fo r a given sysclk (bus) frequency, the pll configuration signals se t the internal cpu and vco frequency of operation. the pll configuration for the pc7457 is shown in table 18 for a set of exam- ple frequencies. in this example, shaded cells represent settings that, for a given sysclk frequency, result in core and/or vco frequencies that don?t comply with the 1 ghz column in table 8 on page 20 . table 18. pc7457 microprocessor pll configuration example for 1267 mhz parts pll_cfg[0:4] example bus-to-core frequency in mhz (vco frequency in mhz) bus-to-core multiplier core-to-vco multiplier bus (sysclk) frequency 33.3 mhz 50 mhz 66.6 mhz 75 mhz 83 mhz 100 mhz 133 mhz 167 mhz 01000 2x 2x 10000 3x 2x 10100 4x 2x 667 (1333) 10110 5x 2x 667 (1333) 835 (1670) 10010 5.5x 2x 733 (1466) 919 (1837) 11010 6x 2x 600 (1200) 800 (1600) 1002 (2004) 01010 6.5x 2x 650 (1300) 866 (1730) 1086 (2171) 00100 7x 2x 700 (1400) 931 (1862) 1169 (2338) 00010 7.5x 2x 623 (1245) 750 (1500) 1000 (2000) 1253 (2505) 11000 8x 2x 600 (1200) 664 (1328) 800 (1600) 1064 (2128) 01100 8.5x 2x 638 (1276) 706 (1412) 850 (1700) 1131 (2261) 01111 9x 2x 600 (1200) 675 (1350) 747 (1494) 900 (1800) 1197 (2394) 01110 9.5x 2x 633 (1266) 712 (1524) 789 (1578) 950 (1900) 1264 (2528) 10101 10x 2x 667 (1333) 750 (1500) 830 (1660) 1000 (2000) 10001 10.5x 2x 700 (1400) 938 (1876) 872 (1744) 1050 (2100)
52 pc7457/47 [preliminary] 5345b?hirel?02/04 notes: 1. pll_cfg[0:4] settings not listed are reserved. 2. the sample bus-to-core frequencies shown are for reference onl y. some pll configurations may select bus, core, or vco frequencies which are not useful, not suppor ted, or not tested for by the pc7455; see ?clock ac specifications? on page 20. for valid sysclk, core, and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly and the pll is disabled. however, the bus interface unit requires a 2x clock to function. therefore, an additional signal, ext_qual, must be driv en at one-half the frequency of sysclk and offset in phase to meet the required input setup t ivkh and hold time t ixkh (see table 9 on page 22). the result is that the processor bus frequency is one-half sysclk while the internal proc essor is clocked at sysclk frequency. this mode is intended for fa ctory use and emulator tool use only. note: the ac timing specifications given in th is document do not apply in pll-bypass mode. pll_cfg[0:4] example bus-to-core frequency in mhz (vco frequency in mhz) bus-to-core multiplier core-to-vco multiplier bus (sysclk) frequency 33.3 mhz 50 mhz 66.6 mhz 75 mhz 83 mhz 100 mhz 133 mhz 167 mhz 10011 11x 2x 733 (1466) 825 (1650) 913 (1826) 1100 (2200) 00000 11.5x 2x 766 (532) 863 (1726) 955 (1910) 1150 (2300) 10111 12x 2x 600 (1200) 800 (1600) 900 (1800) 996 (1992) 1200 (2400) 11111 12.5x 2x 600 (1200) 833 (1666) 938 (1876) 1038 (2076) 1250 (2500) 01011 13x 2x 650 (1300) 865 (1730) 975 (1950) 1079 (2158) 11100 13.5x 2x 675 (1350) 900 (1800) 1013 (2026) 1121 (2242) 11001 14x 2x 700 (1400) 933 (1866) 1050 (2100) 1162 (2324) 00011 15x 2x 750 (1500) 1000 (2000) 1125 (2250) 1245 (2490) 11011 16x 2x 800 (1600) 1066 (2132) 1200 (2400) 00001 17x 2x 850 (1900) 1132 (2264) 00101 18x 2x 600 (1200) 900 (1800) 1200 (2400) 00111 20x 2x 667 (1334) 1000 (2000) 01001 21x 2x 700 (1400) 1050 (2100) 01101 24x 2x 800 (1600) 1200 (2400) 11101 28x 2x 933 (1866) 00110 pll bypass pll off, sysclk clocks core circuitry directly 11110 pll off pll off, no core clocking occurs table 18. pc7457 microprocessor pll configuration example for 1267 mhz parts (continued)
53 pc7457/47 [preliminary] 5345b?hirel?02/04 4. in pll-off mode, no clocking occurs insi de the pc7455 re gardless of the sysclk input. the pc7457 generates the clock for the external l3 synchronous data srams by divid- ing the core clock frequency of the pc7457. the core-to-l3 frequency divisor for the l3 pll is selected through the l3_clk bits of the l3cr register. generally, the divisor must be chosen according to the frequency supported by the external rams, the fre- quency of the pc7457 core, and timing analysis of the circuit board routing. table 19 shows various example l3 clock fr equencies that can be obtained for a given set of core frequencies. notes: 1. the core and l3 frequencies are for reference only. no te that maximum l3 frequency is design dependent. some examples may represent core or l3 frequencies which are not useful, not supported, or not tested for the pc7457; see ?l3 clock ac specifications? on page 24 for valid l3_clk frequencies and for more information regarding the maximum l3 frequency. 2. these core frequencies are not supported by all speed grades; see table 8 on page 20. table 19. sample core-to-l3 frequencies (1) core frequency (mhz) 22.533.544.555.566.577.58 500 250 200 167 143 125 111 100 91 83 77 71 67 63 533 266 213 178 152 133 118 107 97 89 82 76 71 67 550 275 220 183 157 138 122 110 100 92 85 79 73 69 600 300 240 200 171 150 133 120 109 100 92 86 80 75 650 325 260 217 186 163 144 130 118 108 100 93 87 81 666 333 266 222 190 167 148 133 121 111 102 95 89 83 700 350 280 233 200 175 156 140 127 117 108 100 93 88 733 367 293 244 209 183 163 147 133 122 113 105 98 92 800 400 320 266 230 200 178 160 145 133 123 114 107 100 866 433 347 289 248 217 192 173 157 145 133 124 115 108 933 467 373 311 266 233 207 187 170 156 144 133 124 117 1000 500 400 333 285 250 222 200 182 166 154 143 133 125 1050 (2) 525 420 350 300 263 233 191 191 175 162 150 140 131 1100 (2) 550 440 367 314 275 244 200 200 183 169 157 147 138 1150 (2) 575 460 383 329 288 256 209 209 192 177 164 153 144 1200 (2) 600 480 400 343 300 267 218 218 200 185 171 160 150 1250 (2) 638 500 417 357 313 278 227 227 208 192 179 167 156 1300 (2) 650 520 433 371 325 289 236 236 217 200 186 173 163
54 pc7457/47 [preliminary] 5345b?hirel?02/04 pll power supply filtering the av dd power signal is provided on the pc7457 to provide power to the clock gener- ation pll. to ensure stability of the internal cloc k, the power supplied to the av dd input signal should be filtered of any noise in the 500 khz to 10 mhz resonant frequency range of the pll. a circuit similar to the one shown in figure 29 using surface mount capacitors with minimum effective se ries inductance (esl) is recommended. the circuit should be placed as close as possible to the av dd pin to minimize noise cou- pled from nearby circuits. it is often possible to route directly from the capacitors to the av dd pin, which is on the periphery of the 360 cbga footprint and very close to the periphery of the 483 cbga footprint, without the inductance of vias. the pll power supply filter provided in the pc7457 risc microprocessor hardware specifications has been found to be less e ffective for rev 1.1 devices with the low core voltages described in this specification. as a result, the recommended value for the resistor in the circuit is being evaluated and a new recommendation is indicated in figure 31. motorola continues to evaluate the fil- tering requirements of the pc7457 and will make updated recommendations as needed. note that this recommendation a pplies to rev. 1.1 devices only. figure 31. pll power supply filter circuit decoupling recommendations due to the pc7457 dynamic power management feature, large address and data buses, and high operating frequencies, the pc7457 can generate transient power surges and high frequency noise in its power supply, es pecially while driving large capacitive loads. this noise must be prevented from reaching other components in the pc7457 system, and the pc7457 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , ov dd , and gv dd pin of the pc7457. it is also recommended that these decoupling capacitors receive their power from separate v dd , ov dd /gv dd , and gnd power planes in the pcb, utilizing short tr aces to minimize inductance. these capacitors should have a value of 0.01 or 0.1 f. only ceramic surface mount technology (smt) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993) and contrary to previous rec- ommendations for decoupling motorola microp rocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , gv dd , and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bul k capacitors should have a low equivalent series resistance (esr) rating to ensu re the quick response time necessary. they should also be connected to the power and gr ound planes through two vias to minimize inductance. suggested bulk capacitors: 100 ? 330 f (avx tps tantalum or sanyo oscon). v dd 400 ? 2.2 f 2.2 f gnd av dd low esl surface mount capacitor
55 pc7457/47 [preliminary] 5345b?hirel?02/04 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , gv dd , and gnd pins in the pc7457. if the l3 interface is not used, gv dd should be connected to the ov dd power plane, and l3vsel should be connected to bvsel; the remainder of the l3 interface may be left unterminated. output buffer dc impedance the pc7457 processor bus and l3 i/o drivers are characterized over process, voltage, and temperature. to measure z0, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 30 on page 50). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held low, sw2 is closed (sw1 is open), and rn is trimmed until the voltage at the pad equals ov dd /2. rn then becomes the resistance of the pull-down devices. when data is held high, sw1 is closed (sw2 is open), and rp is trimmed until the voltage at the pad equals ov dd /2. rp then becomes the resistance of the pull-up devices. rp and rn are designed to be close to each other in value. then, z0 = (rp + rn)/2. figure 32. driver impedance measurement table 20 summarizes the signal impedance results. the impedance increases with junc- tion temperature and is relatively unaffected by bus voltage. table 20. impedance characteristics with v dd = 1.5v, ov dd = 1.8v 5%, t j = 5 - 85 c impedance processor bus l3 bus unit z 0 typical 33 ? 42 34 ? 42 ? maximum 31 ? 51 32 ? 44 ? ov dd ognd sw2 sw1 rn rp pad data
56 pc7457/47 [preliminary] 5345b?hirel?02/04 pull-up/pull-down resistor requirements the pc7457 requires high-resistive (weak: 4.7 k ? ) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the pc7457 or other bus masters. these pins are ts , artry , shdo , and shd1 . some pins designated as being for factory test must be pulled up to ovdd or down to gnd to ensure proper device operation. for the PC7447, 360 bga, the pins that must be pulled up to ovdd are lssd_mode and test[0:3]; the pins that must be pulled down to gnd are l1_tstclk and test[4]. for the pc7457, 483 bga, the pins that must be pulled up to ovdd are lssd_mode and test[0:5]; the pins that must be pulled down are l1_tstclk and test[6]. the ckstp_in signal should likewise be pulled up through a pull-up resistor (weak or stronger: 4.7 ? 1 k ? ) to prevent erroneous assertions of this signal. in addition, the pc7457 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7 ? 1 k ? ) if it is used by the system. this pin is ckstp_out . if pull-down resistors are used to configure bvsel or l3vsel, the resistors should be less than 250 ? (see table 16 on page 40). because pll_cfg[0:4] must remain stable during normal operation, strong pull-up and pull-down resistors (1 k ? or less) are rec- ommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise or noise coupling. during inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. because the pc7457 mu st continually monitor these signals for snooping, this float condition may cause exce ssive power draw by the input receivers on the pc7457 or by other receivers in the system. it is recommended that these signals be pulled up through weak (4.7 k ? ) pull-up resistors by the system , or that they may be oth- erwise driven by the system during inactive periods of the bus. the snooped address and transfer attribute inputs are a[0:35], ap[0:4], tt[0:4], ci , wt , and gbl . if extended addressing is not used, a[0:3] are unused and must be pulled low to gnd through weak pull-down resistors. if the pc7457 is in 60x bus mode, dti[0:3] must be pulled low to gnd through weak pull-down resistors. the data bus input receivers are normally turned off when no read operation is in progress and, therefore, don?t require pull-up resistors on the bus. other data bus receiv- ers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the syst em. the data bu s signals are d[0:63] and dp[0:7]. if address or data parity is not used by the system, and the respective parity checking is disabled through hid0, the input receivers fo r those pins are disa bled, and those pins don?t require pull-up resistors and should be left unconnected by the system. if all parity generation is disabled through hid0, then all parity checking should also be disabled through hid0, and all parity pins may be left unconnected by the system. the l3 interface does not normally require pull-up resistors.
57 pc7457/47 [preliminary] 5345b?hirel?02/04 jtag configuration signals boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all processors that imple- ment the powerpc architecture. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset perfor- mance will be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to i ndependently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures , or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 31 allows the cop port to independently assert hreset or trst , while ensuring that t he target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset through a 0 ? isolation resistor so that it is as serted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during power-on. while motor- ola recommends that the cop header be designed into the system as shown in figure 31 on page 54, if this is not possible, the isol ation resistor will allow future access to trst in the case where a jtag interface may need to be wired onto the system in debug situations. the cop header shown in figure 31 adds many benefits ? breakpoints, watchpoints, register and memory examination/modifi cation, and other standard debugger features are possible through this interface ? and can be as inexpensive as an unpopulated foot- print for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. there is no standardized way to number the cop header shown in figure 31; conse- quently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to- bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal plac ement recommended in figure 31 is com- mon to all known emulators. the qack signal shown in figure 31 is usually connected to the pci bridge chip in a system and is an input to the pc7457 informing it that it can go into the quiescent state. under normal operation this occurs during a low-power mode selection. in order for cop to work, the pc7457 must see this signal asserted (pulled down). while shown on the cop header, not all emulator products drive this signal. if the product does not, a pull-down resistor can be populated to assert this signal. additionally, some emulator products implement open-drain ty pe outputs and can only drive qack asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. note that the pull-up and pull-down resistors on the qack signal are mutually exclusive and it is never necessary to populate both in a system. to preserve correct power-down operation, qack should be merged via logic so that it also can be driven by the pci bridge.
58 pc7457/47 [preliminary] 5345b?hirel?02/04 figure 33. jtag interface connection notes: 1. run/stop , normally found on pin 5 of the cop header, is not im plemented on the pc7457. connect pin 5 of the cop header to ov dd with a 10 k ? pull-up resistor. 2. key location; pin 14 is not physically present on the cop header. 3. component not populated. populate only if debug tool does not drive qack . 4. populate only if debug tool uses an open-drain type output and does not actively deassert qack . 5. if the jtag interface is implemented, connect hreset from the target source to trst from the cop header though an and gate to trst of the part. if the jtag interface is not implemented, connect hreset from the target source to trst of the part through a 0 ? isolation resistor. 6. though defined as a no-connect, it is a common and recommended practice to use pin 12 as an additional gnd pin for improved signal integrity. hreset hreset hreset 13 sreset sreset sreset 11 vdd_sense 6 5 (1) 15 2 k ? 10 k ? 10 k ? 10 k ? ov dd ov dd ov dd ov dd chkstp_in chkstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 14 (2) key qack ov dd ov dd ov dd trst 10 k ? 10 k ? 10 k ? 10 k ? ov dd qack qack chkstp_out chkstp_out 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin cop connector physical pin out 10 k ? (4) ov dd 1 2 k ? (3) 0 ? (5) 12 (6) nc from target board sources (if any) cop header
59 pc7457/47 [preliminary] 5345b?hirel?02/04 definitions datasheet status description life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can r easonably be expected to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nify atmel for any damages resulting from such improper use or sale. table 21. datasheet status datasheet status validity objective specification this datasheet contains target and goal specifications for discussion with customer and application validation. before design phase target specification this datasheet contains target or goal specifications for product development. valid during the design phase preliminary specification -site this datasheet contai ns preliminary data. additional data may be published later; could include simulation results. valid before characterization phase preliminary specification -site this datasheet also contains characterization results. valid before the industrialization phase product specification this datasheet contains final product specification. valid for production purposes limiting values limiting values given are in accordance with the absolute maxi mum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics secti ons of the specification is not implied. exposure to limitin g values for extended periods may affect device reliability. application information where application information is given, it is advis ory and does not form part of the specification.
60 pc7457/47 [preliminary] 5345b?hirel?02/04 ordering information note: 1. for availability of the different versions, contact your local atmel sales office. pc 7457 v g u 1000 lx prefix type screening level (1) u: upscreening revision level (1) rev. b, c application modifier (1) l: 1.3v 50 mv n: 1.1v 50 mv max internal processor speed (1) 933 mhz 1000 mhz 1200 mhz (tbc) temperature range: t j (1) prototype (x) v: -40?c, 110?c m: -55?c +125?c package g: cbga pc 7447 v g u 1000 lx prefix type screening level (1) u: upscreening revision level (1) rev. b, c application modifier (1) l: 1.3v 50 mv n: 1.1v 50 mv max internal processor speed (1) 933 mhz 1000 mhz 1200 mhz (tbc) temperature range: t j (1) prototype (x) v: -40?c, 110?c m: -55?c +125?c package g: cbga gh: hitce (tbc)
61 pc7457/47 [preliminary] 5345b?hirel?02/04 document revision history table 22 provides a revision histor y for this hardware specification. table 22. document revision history revision number substantive change(s) b figure 9 on page 22: corrected pin lists for input and output ac timing to correctly show hit as an output-only signal added specifications for 1267 mhz devices; removed specs for 1300 mhz devices. changed recommendations regarding use of l3 clock jitter in ac timing analysis in section ?l3 clock ac specifications? on page 24; the l3 jitt er is now fully comprehended in the ac timing specs and does not need to be included in the timing analysis
62 pc7457/47 [preliminary] 5345b?hirel?02/04
i pc7457/47 [preliminary] 5345b?hirel?02/04 table of contents features .............. .............. .............. ............... .............. .............. ...........1 description ......... .............. .............. ............... .............. .............. ...........1 screening ............ .............. .............. ............... .............. .............. .......... 2 block diagram ........... ................. ................ ................. .............. ...........3 general parameters ............ .............. .............. .............. .............. .........4 features .............. .............. .............. ............... .............. .............. ...........4 signal description .............. ................ ................. ................ ..............10 detailed specification ........ ................ ................. ................ ..............11 scope ................ .............. .............. .............. .............. .............. ............11 applicable documents ....... ................ ................. ................ ..............11 requirements ................. .............. .............. .............. .............. ............11 general ................................................................................................................ 11 design and construction .................................................................................... 11 absolute maximum ratings ................................................................................ 11 recommended operating conditions................................................................. 12 thermal characteristics ...................................................................................... 13 electrical characteristics ..... ................ ................. ................ ............19 static characteristics .......................................................................................... 19 dynamic characteristics ..................................................................................... 20 preparation for delivery ..... ................ ................. ................ ..............37 handling ............ .............. .............. .............. .............. .............. ............37 package mechanical data .. ................ ................. ................ ..............38 package parameters for the PC7447, 360 cbga .............................................. 38 pin assignment ......... ................. ................ .............. .............. ............39 pinout listings......... ................ ................. ................ .............. ........... 40 mechanical dimensions for the pc 7447, 360 cbga ......................43 substrate capacitors fo r the PC7447, 360 cbga . .............. ............44
ii pc7457/47 [preliminary] 5345b?hirel?02/04 package parameters for the pc7457, 483 cbga ............ ................44 mechanical dimensions for the pc 7457, 483 cbga .......................49 substrate capacitors fo r the pc7457, 483 cbga..... .............. ........ 50 system design information .... ................. ................ .............. ........... 51 pll configuration .............. ................ ................. ................ ..............51 pll power supply filtering ................................................................................ 54 decoupling recommendations ........................................................................... 54 connection recommendations........................................................................... 55 output buffer dc impedance ............................................................................. 55 pull-up/pull-down resistor requirements .......................................................... 56 jtag configuration signals ............................................................................... 57 definitions .............. ................ ................ ................. ................ ........... 59 datasheet status description .............. ................. ................ ............59 life support applications ... ................ ................. ................ ............. 59 ordering information........... ................ ................. ................ ............. 60 document revision history ................. ................. ................ ............61
iii pc7457/47 [preliminary] 5345b?hirel?02/04
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